This paper investiGates the possibility and effectiveness of multi-mode vibration control of a plate through real-time (FPGA) (Field Programmable Gate Array) implementation. This type of embedded system offers true parallel and high throughput computation abilities. The control object is an aluminum panel, clamped to a Perspex box’s upper side. Two types of control laws are studied. The first belongs to non-model based control. This control law is designed to generate active damping within the designed bandwidth. The second control law is model based H-infinity robust control. A system identification process is needed before the controller comes out. Each of the control laws is implemented on a (FPGA) target, which is powerful enough to achieve high throughput control loop rates. The experimental control results demonstrate that the non-model based control law has sufficient authority to suppress the interesting modes. The model-based robust control law’s control performance is not so positive compared to the previous method. Therefore, it is not recommended for this application. College of Automation, Nanjing University of Posts and Telecommunications, Nanjing, China

The evolution of today's application technologies requires a certain level of robustness, reliability and ease of integration. We choose the Fields Programmable Gate Array ((FPGA)) hardware description language to implement the facial recognition algorithm based on "Eigen faces" using Principal Component Analysis. In this paper, we first present an overview of the PCA used for facial recognition, then use a VHSIC Hardware Description Language (VHDL) simulation and design platform, which is the ISE. We describe the operation of each block and implement, thereafter, the computation of the global centered images. This corresponds to the first step of the PCA algorithm to assess its performance. The comparison of the results of this implementation with that of MATLAB confirmed the operability and effectiveness of this method for centralizing images. We also implemented the last part of this algorithm which is the computation of the Manhattan distance. The tests have given very satisfactory results.

In this work, the design of a low-cost, Field Programmable Gate Array ((FPGA))-based digital hardware platform that implements image processing algorithms for real-time distance measurement is presented. Using embedded development kit (EDK) tools from Xilinx, the system is developed on a spartan3 / xc3s400, one of the common and low cost Field Programmable Gate Arrays from the Xilinx Spartan family. Latency of the hardware is less than 100μ s in 5000 clock cycles with 50MHz maximum frequency which is way less than MATLAB software performance about 82ms. Simulation and experimental results clearly indicate the potential of the presented FGPA-based platform for real-time distance measurement of images acquired from our camera setup. Thus, this platform can be used in any system with the needs of real-time or semi real-time machine vision.

In this work, a useful equipment for recording and analysing of random processes was developed based on Field Programmable Gate Array ((FPGA)). The system covers a range of different applications in the nuclear Fields of study. The system is potentially applicable for zero power reactor noise analysis, time coincidence of stochastic events, dead time estimation, and probability distribution function of random processes. The designed and constructed system was tested and validated by generated pseudorandom processes. Some of the basic analysing methods of random processes were checked and verified experimentally. As the performance of the system depends on the hardware, the designed architecture is implemented on a typical system. The best performance is reported in the text.

Reversible logic circuits have found emerging attentions in nanotechnology, optical computing, quantum computing and low power design. A Programmable logic Array (PLA) is a universal circuit which is used to implement combinational logic circuits. The main part of a PLA is its AND Array. In this study we propose two types of optimized reversible Programmable logic Array (RPLA) circuits. The first type is based on a “2-to-4” AND Array, and is proposed for the first time. The second type is based on a “3-to-8” AND Array. For each type, we bring some different designs. These circuits are compared with the existing counterparts in terms of number of constant inputs and garbage outputs, delay and the quantum cost and are shown that all parameters in proposed circuits are improved.

In this paper, a 2 GHz counter is implemented on a low-cost XC6SLX9-2FTG256C Field-Programmable Gate Array ((FPGA)) chip from the Spartan6 family with a 500 ps resolution. Since the hardware resources contained in this chip are not sufficient to implement this design, and also the inherent delays of the hardware resources inside the chip are about few nanoseconds, achieving this accuracy is very important. The architecture used in this research is based on the phase difference clocks that has been implemented after optimization. To achieve this accuracy, it is necessary to design and implement counters with high clock frequency, low jitter and low skew, without dependence on hold time and setup time. Alternative hardware resources have also been used to compensate for the lack of hardware resources required to implement routing clocks.

Power amplifiers (PAs) are inherently nonlinear elements and digital predistortion is a highly cost-effective approach to linearize them. Although most existing architectures assume that the PA has a memoryless nonlinearity, memory effects of the PAs in many applications, such as wideband code-division multiple access (WCDMA) or orthogonal frequency-division multiplexing (OFDM), can no longer be ignored and memoryless predistortion has limited effectiveness.In this paper, a novel digital predistorter based on the Hammerstein structure has been proposed for linearization of radio frequency power amplifiers with memory effect. Designing the Hammerstein model based digital predistorter has been done using an accurate Wiener model of the power amplifier. The proposed digital predistorter has many advantages such as low computational complexity, low memory space and simple implementation. The elimination of nonlinear effects and constructing accurate behavioral model, which is the exact inverse of a power amplifier characteristic, have been demonstrated by simulating 64 QAM constellation diagram in Matlab. In order to validate the proposed predistorter, it is implemented in Kintex (FPGA) using Vivado HLS and acceptable results have been obtained.